In a manufacturing process of a semiconductor integrated circuit, an etching process refers to a process for selectively removing a layer formed on a substrate through an oxidation process or a thin film deposition process.
In addition, the etching process is used to remove a selected portion of a wafer surface, and is performed after a photolithography process in a semiconductor process. In detail, according to the etching process, a photoresist (PR) pattern that is formed through the photolithography process is used as a mask, a portion under the mask and a portion exposed to an exterior are subject to different chemical reactions, and an unnecessary portion is removed from the wafer surface by using gas, acid, or alkali chemical materials, thereby forming a fine circuit pattern. Such a pattern forming procedure is repeatedly performed relative to each pattern layer.
The photolithography process is classified into an optical lithography technology and a radiation lithography technology. The optical lithography technology employs an ultraviolet (UV) beam, and the radiation lithography technology employs an x-ray beam, an electron beam, or an ionization beam.
Photoresist patterns formed by the photolithography process are used as masks, and a portion under the mask and a portion exposed to an exterior are subject to different chemical reactions, so that a portion that is not protected by the mask is etched away during the photolithography process.
Through the above etching process, diffusion and ion implantation areas are determined, and a metallization process is performed. The etching process is divided into a wet etching process and a dry etching process according to schemes of removing an oxide layer. The wet etching process is most widely used in the semiconductor process. In other words, the etching process is used in the surface polishing of a cut wafer, wafer cleaning before the growing of a thermal oxidation layer or an epitaxial silicide layer (ESL), and the manufacturing of a semiconductor device having a line width of at least 3 μm.
Although the wet etching process can provide superior selectivity by using an etching solution having selectivity, the wet etching process causes an undercut phenomenon due to isotropic properties, so that the wet etching process is not suitable when it is necessary to form a fine pattern.
The undercut phenomenon is caused because the etching solution flows into the lower portion of a mask to form an oxidation pattern in the wet etching process.
FIG. 1 is a view showing a pattern that is isotropically etched according to the related art, and FIGS. 2 to 5 are views showing etched profiles according to the conventional isotropic over etching.
It can be recognized from FIG. 1 that the sectional surface of a fine pattern is shown in the shape of a trapezoid after performing the isotropic etching. This is because an etching solution is infiltrated into the lower portion of a photoresist pattern 110 to continuously etch the upper portion of a layer to be etched (hereinafter, referred to as an “etching layer”) through the etching process, so that the etching layer has a gradually narrowed width in the upper portion thereof to be in the shape of a trapezoid. Such an etching process is continuously performed while etching the etching layer in the round shape until the surface of the semiconductor substrate 130 is exposed. As the above round shape is expanded, undercut below the photoresist layer becomes more severe. The formation range of the undercut cannot be detected until the photoresist layer is removed.
Referring to FIGS. 2 to 5, the shape of the edges of an oxide layer pattern represents the degree of undercut, and an etched profile is shown in FIGS. 2 to 5 as the etching process is performed. The etched fine pattern 120 formed on the photoresist pattern 110 and the semiconductor substrate 130 has different edge shapes according to the degree of an inclined plane. Color bands are created according to the thickness of an oxide layer on the etched incline plane, and the degree of undercut may be recognized by using the width of a black band created on the circumference of the oxide layer pattern.
FIG. 6 is a photographic view showing the shape of a lead of a fine pattern employing isotropic etching according to the related art. Referring to FIG. 6, if isotropic etching is performed such that the height of the internal lead becomes 7.5 μm on an assumption that the pitch width (not shown) of an internal lead becomes 25 μm on a chip-on-film employing isotropic etching according to the related art, undercut occurs by the length of 4.9 μm in the upper portion of the internal lead and the length of 12.75 μm in the lower portion of the internal lead. Accordingly, the width of the upper portion of the internal lead is excessively narrowed, so that the fine pattern has the shape of a trapezoid.
As described above, according to the conventional isotropic etching scheme, since undercut is caused, a pattern cannot be realized in the case of a flexible printed circuit (FPC), a tape carrier package (TCP), and a chip on film (COF) requiring the fine pattern having a lead top width of at least 6 μm. In addition, since the sectional surface of the fine pattern has a trapezoid shape or a triangular shape, the bonding between the fine pattern and a semiconductor integrated circuit is difficult.